3D chip stacking technology is currently not going to come in a big way, with only Intel Foveros accessing the market for Lakefield CPUs, and other Zen3-based storage devices waiting for the wings. But at this year’s Hot Chips conference, AMD is already setting where it intends to go from here, with proud ideas on how to use this technology.
The 3D V-Cache shown by AMD at Computex is a (simple) easy addition to L3 storage for the Ryzen 9 5900X, bringing a ~ 15% performance boost to games. 3D-stacking layout allowed AMD to use a production process that allows for the most complete SRAM of high mortality, equivalent to 64 MB in the space directly above 32 MB on the death base which should have been silicon suitable for both cache and compute.
All of this was done using through-silicon vias (TSVs), connected by a direct direct copper-to-copper packaging that is much closer than "traditional" microbump technology.
AMD ranks 9 micron bump pitch with its hybrid direct bonding technology; by comparison, Intel Foveros operated on an order of 50 microns while operated at Lakefield, a key comparison point used for AMD's claim of 3x performance gains and 15x higher magnification for its connection compared to the "anonymous single" form factor. 3D ".
Team Blue also has a mass of 36 microns quoted in its upcoming Foveros Omni technology to be used in Meteor Lake CPUs, and 10 microns at Foveros Direct, a hybrid solution that is in direct contrast to what AMD is showing here.
However, both are targeted by 2023, with AMD predicting that their 3D-integrated chips will be in high production by the end of this year.
The company also works with TSMC on more sophisticated 3D designs, with the aim of inserting CPU cores into each other, separating CPU macroblocks (such as low cache levels) between different layers, or descending to a regional cut level.
Stacking compute silicon in particular brings unique difficulty in providing power to high diets and removing low temperatures - one of the reasons why AMD's 3D V-Cache is only mounted above the base death cache, leaving only CPU cores.
Of course, all of this depends on how much energy, efficiency, space and cost (PPAC) metrics can be improved - and, of course, if the TSMC can continue to bring their high-level strategies into mass production.